A security unit has been proposed to detect these attacks and mitigate the consequent loss by guiding the control units of the corresponding buffers to either isolate or mask the attacked buffers in runtime. These attacks contribute to the degradation of network performance and may even create deadlocks, which can raise serious concerns in time critical systems. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. An initial implementation of this programming model is also presented, which leverages a set of extensions to a MPSoC-specific OpenMP compiler and run-time environment.Ī novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Furthermore, we identify a set of programming abstractions useful to associate the notion of priority to each running task in the system.
We designed NoC hardware support, low-level middleware and APIs which enable QoS control at the application level.
Flow free bridges 9x9 level 25 software#
In this paper we consider an integrated hardware/ software approach for delivering QoS at the application level. The complex and non-uniform nature of network traffic generated by parallel applications running on a large number of possibly heterogeneous IPs makes a strong case for providing Quality of Service (QoS) support for traffic treams over the NoC infrastructure. Embedded applications, in turn, are becoming extremely sophisticated, and often require guaranteed levels of service and performance. Networks-on-Chip (NoCs) are being increasingly considered as a central enabling technology to communication-centric designs as more and more IP blocks are integrated on the same SoC. The conducted experiments show the efficiency of the proposed method in terms of throughput, latency and jitter for a real time application sharing communication resources with best-effort applications.
In this work, we propose a hardware/software approach to achieve applications composability by means of QoS management mechanisms at the software level. As the NoC is the main shared component in NoC-based MPSoCs, quality-of-service (QoS) mechanisms are mandatory to meet application requirements in term of communication. Such a feature is referred to as composability. To ensure applications requirements are met, mechanisms are necessary for ensuring proper isolation. However, as the number of applications executing simultaneously increases, the performance of such applications may be affected due to resources sharing. The computational power of these architectures enables the simultaneous execution of several applications, with different time constraints. The use of Networks-on-chip (NoCs) provides to these platforms scalability and support for parallel transactions. Multiprocessors systems on chip (MPSoCs) have become the de-facto standard in embedded systems. This work highlights the need to integrate NoC and MPSoC design efforts in a unified framework. Using the priority scheme developed in this work, applications executing in the MPSoC achieve the performance requirements. Results shows that, even with the huge available bandwidth offered by NoCs, such interconnection architecture is not capable to meet QoS constraints when flows compete for common resources inside the NoC. Such API hides the interconnection complexity from programmer and provides efficient design space exploration to meet the QoS application requirements. This work bridges the hardware/software gap, exploring the integration of low-level NoC services into an application programming interface (API). An important issue in MPSoC design is QoS, since applications running in such systems may have tight timing constraints, as video processing or fast communication protocols. A lot of research effort has been conducted in the last years in NoC and MPSoC designs, but few works address the gap between the NoC infrastructure and the MPSoC software applications. The use of NoCs in complex MPSoCs is a reality in academic researches and industrial designs.
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